Demodulator for pulse width modulated signals

ABSTRACT

The subject disclosure relates to a frequency demodulator. The demodulator produces two pulse trains from the transitions which are square wave trains with one train being inverted with respect to the other. These transitions define &#39;&#39;&#39;&#39;transition periods.&#39;&#39;&#39;&#39; During During the first transition period, a capacitor is discharged so that at the end of that period, it provides a signal that is a function of the time width of the first odd transition period of the first train of square waves. During the second even transition period, another capacitor is discharged so that at the end of this period the capacitor provides a signal which is a function of the time length of the second transition period. Thus, the two trains provide alternately a voltage level that is a function of alternate transition periods. These signals are then added to produce a quantitized version of the frequency modulation.

United States Patent [72] Inventor Lynn P. West 2,904,683 9/1959 Meyer329/104X A 1 N0 53:3 Primary Examiner-Roy Lake 53 Janm 1969 AssistantExaminer-Lawrence .l. Dahl [45] Patented 1971 Attorneys-Hanifin andJancin and Vincent W. Cleary [73] Assignee International BusinessMachines Corporation ABSTRACT: The subject disclosure relates to afrequency I demodulator. The demodulator produces two pulse trains [54]DEMODULATOR FOR PULSE wmTH from the transitions which are square wavetrains with one MODULATEI) SI N L r n bsizzaee t L e t..tQJl 52-9th9iIh?t ensir 5 Claims 3Drawing Figs. lions define transition periods. Duringthe first transition per od, a capacitor is d scharged so that at theend of that [52] U.S.Cl 329/104, paged, ditvgrgyigvesd a" Signal fi' 'i'fI aEfi 'g gg' 55 329/106 width of the first odd transition period ofthe first train of hiltquare waves During the second even transitionperiod Fleld ofSearch another capacitor is discharged so that at the endof 328/112 140; 329/104, 106, 107 period the capacitor provides a signalwhich is a function of the time length of the second transition period.Thus, the two [56] References cued trains provide alternately a voltagelevel that is a function of UNITED STATES PATENTS alternate transitionperiods. These signals are then added to 2,716,189 8/ i955 Ayres329/104X produce a quantitized version of the frequency modulation.

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LYNN R WEST ATTORNE'Y EMOIEULATOR FOR PULSE wmrr-r MODULA'IED SEGNALSBACKGROUND OF THE INVENTION l. Field of invention Frequency modulators.

2. Description of the Prior Art Prior demodulators have provided ahyperbolic waveform that is a function of the time between transitions.At the end of a sawtooth, the waveform is sampled by a short pulse andheld to provide a form of quantitized waveform. These short pulses forsampling must occur at the same rate as the transitions and must beachieved by very fast switching. Since the sampling is done at the FMrate, the PM will feed through to the output unless rather expensivefiltering is accomplished. The subject disclosure does not sample butrather operates on two trains of square waves to produce voltage levels.Consequently, when these two trains of square-waves are added, fastswitching is not required and, in addition, the feed through from theFM, if any, would be far less than prior demodulators. As a result ofthis feed through, filters were required that are not necessary in thedemodulator disclosed herein.

SUMMARY OF THE INVENTION It is an object of the invention to provide anew and improved demodulator.

A further objectof the invention is the provision of a new and improveddemodulator for frequency demodulation with a minimum of FM feed-throughat the output of the demodulater.

A still further object of the invention is to provide a frequencydemodulator with a minimum of filtering required at the output.

A still further object of the invention is the provision of a frequencydemodulator, the output of which can be applied directed to a televisionmonitor.

The above objects of the present invention are accomplished by afrequency demodulator that receives a train of pulses that define aplurality of pulse time periods. It further includes a first means whichdevelops a first signal having portions that have an amplitude which isthe function of the time length of even alternate pulse time periods.The demodulator further includes a second means which develops a secondsignal having portions that have an amplitude which is the function ofthe odd alternate pulse time periods. The respective portions of thesetwo signals are then summed so that the output consists alternately ofthe first signal and then the second signal. Since there is no highspeed sampling, as done in the prior art, at the PM rate or faster,there is no FM feedthrough and, consequently, no necessity to employrespective filters to remove this feed-through.

nescan non or "run DRAWING FIG. 1 is a schematic diagram partially inblock form of a demodulator embodying the invention.

H6. 2 is a schematic diagram of the AND integrating and holding circuitll) and $9 shown in FIG. 1.

' Fit 3 illustrates waveforms useful in explaining the operation of thedemodulator illustrated in FIG. ll.

GENERAL DESCRIPTION The frequency modulation input, such as waveform ashown in FIG. 3 (a) is applied to the input terminal 8 of thedemodulater circuit shown in FIG. I. The positive rises of pulses aoccurring during the odd intervals defined by the pulses width orduration of waveform a will trigger a single shot 2%, the output ofwhich is on for a predetermined time T as shown for the waveform in FIG.3 (c), This time period T is selected to be only a portion of the pulsetime periods normally defined by the rise and decay angles, and thewidth of the pulses. Both the output of the single shot 2% and theoriginal pulses from the FM are applied to an AND integrating andholding circuit 80. Between time period T of the end of the square waveoutput of single shot 2% and the end of the positive pulses Pi, P3,etc., defining the decay of the odd transition time periods, the circuit40 will integrate by discharging a capacitor and during the even timeperiods P2. P4, etc., circuit 4 0 will have an output provided that isthe function of the odd time periods Pl, l3, etc. This output is appliedto the analogue gate 60 which allows the output of the integratingcircuit 40 to pass to a summing point A during the even transitionperiods.

The PM input a is also applied to an inverter It) to provide an outputsignal b shown in FIG. 3(b). Output b is then applied to a single shot30 which providesan output 41 shown in FIG. 3(d)'that also has a timelength of T. Both single shots 20 and 30 are on the same length of timeDuring the time period between the end of the output of the single shot30 and the end of an even transition time period P2, P4, etc., thecircuit 50 integrates by discharging a capacitor with the integratingending at the end of the even transition time periods. The output of thecircuit 50 (the capacitor) is then held during the odd transition timeperiods, and the analogue gate allows the signal from 50 to pass topoint A during the odd time periods. Thus, the output signal is takenfrom the circuit 40 during the even transition time periods and from thecircuit 50 during the odd transition time periods. In this manner, bydeveloping the signal during every other time period while the othercircuit is providing the signal, there results a minimum of feed-throughof the FM. It will be understood that the invention can be utilized byomitting the single shots 20 and 30, and merely integrating during thewhole time period. The single shots 20 and 30, however, result in morenoise free detection, where the deviation ratio Af/f, m is small.

SPECIFIC DESCRIPTION l The waveforms (a) through (dland (f) through (it)in FIG. 3 are the waveforms at positions a through d and f through k,respectively, shown in FIGS. I and 2. The waveform (e) represents thecorrelative circuit position of waveform (f) in the circuit of FIG. 2,but for the circuit block Ell instead of for the circuit block dll (FIG.2). As stated above, the FM input a, shown in FIG. 3(a) is applied tothe input terminal 8, and thence to single shot 20. In FIG. 3, (a) theodd transition time periods defined by the PM are illustrated as P1, P3,P5, etc. The leading edges of these positive going pulses Pl, P3, P5,etc., occurring at the beginning of the odd time periods, turn on thesingle shot delay 20 to produce an output shown as waveform (c) in FIG.3. Single shots 20 and 30 are only sensitive to positive going leadingedges and they are not responsive to negative going trailing edges.These output pulses t,, 1 etc. of waveform (c) are selected to last forthe time period T, as shown in FIG. 3(c), which is less than the timeperiods between the transitions of the pulses Pl, P3, etc. The FM inputis also applied to inverter l0, which produces the output waveform (b)shown in FIG. 3(b), so that there are positive going pulses during theeven alternate transition time periods as illustrated as P2, P4, etc.The leading edge of these positive going pulses triggers the single shot30, which produces pulses t 2 etc. having a time period T that is thesame time duration as for pulses 1,, 1 etc.

If, as stated above, between the end of pulses I 1 etc. from the singleshot 2d and the end of the corresponding odd time period P1, P3, etc.that is, during the time periods Tl, T3, T5, etc. as shown in FIG. 3(f),the AND integrating and holding circuit 4% integrates. During the eventime periods, the output which results in the integration from circuit4d is held by circuit all) and gated by analogue gate fill to thesumming point A.

During the time period between the end of pulses T 71,, etc. at theoutput of the single shot S ll and the end of the corresponding eventime period P2, P4, etc. the AND integrating and holding circuit 5%integrates by discharging a capacitor. The output resulting from thisintegration is held during the odd time periods and gated by analoguegate ill during the odd time periods to the summing point A. Thecircuits 40 and 50 are identical in the preferred embodiment as are thegates 60 and 7%. Therefore, the details of only circuit 40 are shown andillustrated in FIG. 2.

The output (e) of the single shot delay, 20 is applied to the base ofthe transistor T43 through terminal 43a The emitter of the transistorT43 is connected to ground through a charging capacitor C41. TransistorT43 is held on by the pulses t., t etc. shown in 1 10. 3(c). During thistime period T the current through emitter of T43 then maintains thecharging capacitor C41 completely charged. T43 has its emitter connectedin an emitter follower relationship to the base of the buffer transistorT45, which has collector resistor R45 con nected to a positive 12 voltcollector supply. The emitter of transistor T45 is connected through anemitter follower resistor R46 to a negative 6 volt bias supply.

The PM input for waveform (a) is also connected through terminal 42a tom inverter 42 that inverts waveform (a) to produce waveform E. Theinverter 42 applies waveform E to the base of transistor T41 with thebase of T41 being connected through a resistor R41 to a negative biassupply of minus 6 volts. The base of transistor T42 is connected througha resistor R42 to the same negative 6 volt bias supply. The transistorsT41 and T42 have their collectors connected directly together, as wellas their emitters, which are grounded. The collectors of T41 and T42 arealso connected to the base of transistor T44 which is connected througha resistor R43 to a bias supply of +12 volts. In addition, the base oftransistor T44 is connected through a resistor R43 to ground. Theemitter of transistor T44 is connected through a resistor R44 to ground.Transistor T44, when turned on, acts to discharge capacitor C41 and thecollector of T44 is connected to the base of T45, capacitor C41 and theemitter of transistor T41.

The waveform (c) shown in FIG. 3(c) is applied to the base of transistorT42. Further, as stated, the waveform (a) shown in FIG. 3(a), is appliedinverted to the base of T41. Both waveformsfi and (c) are two level orbinary type waveforms. If waveform E is at its low level, it will resultin T41 being turned off or nonconductive. if waveform (c) is at its lowlevel, it will result in T42 being turned off or nonconductive. 1fwaveform (c) is at its high level, T42 will conduct. If either T41 orT42 is conducting, the potential of the base of T44 will be lowered(near ground) sufficiently so as to prevent T44 from conducting. lf,however, both T4 and T42 are turned off or nonconductive, the transistorT44 will be turned on (due to 12V bias connected to R48, which isconnected to the base of T44), thereby discharging capacitor C41.

Thus, during occurrence of pulses t,, etc., (or high level of waveformc) T43 will be on, quickly, charging capacitor C4! at the beginning ofpulses t,, etc. Furthennore, during occurrence of pulses etc., thesepulses render T42 conductive and thus render T44 nonconductive. Duringoccurrence of t,, etc., T41 is rendered nonconductive by the low levelof waveform 5. Between the end of pulses t,, 2 and the end of thecorresponding period P1, P3, etc., transistors T41 and transistor T42are nonconductive and T44 is conducting, thereby discharging capacitorC41 an amount depending on the length of this time period. Thesedischarging periods are defined by pulse T1, T3, etc., of waveform (f)shown in lFlG. 3(f). At the end of the time periods T1, T3, etc., T41will be turned on (by waveform until the next odd time period P1, P3,etc., thus turning off T44 until that time. It will be noted that T42conducts only during the occurrence of pulses etc., as does alsotransistor T43.

Transistor T45 is a buffer and draws virtually no current from capacitorC41 due to the high input impedance of transistor T45. T45 provides anoutput that is a function of the charge on C41. A 2N918 transistor typemay be used as a suitable transistor for T45. The emitter of T45 isconnected through resistor R47 to the collector of transistor T61.

The analogue AND gate 40 comprises a transistor 61 with the signal abeing applied through resistor R62 to the base of the transistor T61.During the odd transition time periods, transistor T61 will beconductive, shorting to ground any outputs from transistor T45 due tothe positive going pulses during periods P1, P3 and P5 being applied tothe base of transistor T61. Thus, during these periods no output will beapplied from T45 to point A. During the odd transition time periods, P2,P4, etc., this transistor T61 will not be rendered conductive bywaveform (a) and the output of transistor T45, which is a function ofthe charge on capacitor C41, will be applied through a resistor 61 to asumming point A.

The AND integrate and hold circuit 50 and gate 71) are identical instructure to the units 40 and 61!), respectively, illustrated in FIG. 3.The signals applied thereto, however, are dif ferent. The correspondinginput terminal 41 would have the waveform (d) applied thereto from theoutput of single shot 30. The input terminal of circuit 50 correspondingto input terminals 42a and 62 would have the waveform (b) from inverter111 as illustrated in FIG. 3(b) applied thereto. As a result of theseconnections, the capacitor C41 would be charged by the transistor T43during the beginning of the even transition time periods P2, P4, etc.,and discharged from the end of the output pulses t etc., of single shot31) and the end of the even periods P2, P4, etc. This discharge periodis illustrated by the pulses T2 and T4, during which transistor T44conducts. During T2, T4, etc., the capacitor corresponding to capacitorC41 will be discharged. The gate will be the same as gate 60; however,it will have the waveform (b) illustrated in FIG. 3(b) applied theretoso that the analogue gate 711 will be conducting during even timeperiods P2 and P4, etc., to prevent the output of circuit 50, from beingapplied through resistor 71 to the summing point A during the even timeperiods. During the odd time periods P1, P3, etc., the transistor ofgate 71) will not be conducting and, therefore, the output of ANDintegrating and holding circuit 50 will be applied through the resistor71 to summing point A.

The signal waveform (i) applied through resistor 61 to point A isillustrated in FIG. 3(i). The signal waveform (j) applied throughresistor 71 to point A is illustrated in FIG. 3(3). The lowest level ofboth of the waveforms is zero and occurs when transistor T61 in gate 60conducts and when a similar transistor in gate 70 conducts.

The summing point A is connected to an emitter follower 80. Moreparticularly transistor 81 has its emitter connected through a resistor32 to ground with an emitter follower output terminal 83. The outputwaveform (k) of this is illustrated in FIG. 3(k).

OPERATION OF THE INVENTION The FM input shown in waveform (a) is appliedto the input terminal 8 and is illustrated in FIG. 3(a). This inputdefines time periods referred to as alternate odd transition timeperiods P1, P3, p5, etc., and alternate even transition time periods P2,P4, etc. The waveform shown in FIG. 3(a) is applied to the single shot20 with the leading edges of P1, p3, etc., starting the time periods.P1, P3 and P5 trigger the single shot delay 20 so as to be turned on asshown in FIG. 3(0) for a predetermined time period T (pulses t i etc.).The output of this single shot is applied to the transistor T43 (ofcircuit 44) so that these positive going pulses turn on this transistor,resulting in fully charging capacitor C41. The original FM shown in FIG.3(a) is applied to inverter 42 to produce a waveform '5 that is appliedto the base of transistor T41. The pulses shown in FIG. 3(c) are alsoapplied to the base of T42. This results in both T41 and T42 being offduring periods defined by pulses T1, T3 and T5, thus raising thepotential on the base of transistor T44 so as to turn this transistor onduring the period defined by pulses T1, T3 and T5. This results in thedischarge of capacitor T41 through transistor T44 during the timeperiods of pulses T1, T3 and T5, which time periods are a function ofthe time width of the transition periods P1, P3 and P5 less the timeperiod T. Thus, the discharge of the capacitors during this time periodis, in effect, an integration although integrators are generallycharging capacitors. The same effect is obtained by discharging. Thecharge is on the capacitor C41 as shown in FIG. 3( g). The dischargeperiods of the capacitor are also illustrated. The partially dischargedcapacitor C41 maintains its level during the even time periods as shownin FIG. 3( g), which level is a function of the previous odd transitiontime period. This level is maintained, since transistor T44 is no longeron, nor is transistor T43 on. Transistor T45, during this period, drawsvirtually no current from capacitor C41 due to its high input impedance.Furthermore, during these even transition time periods, transistor T61is not conducting since the pulses applied to T61 from waveform (a) areno longer highly' positive. Thus, a signal is applied to summing point Aduring the even transition time periods from T45 which signal has alevel from C41 which is a function of the length of the previous oddtransition time period (less the time period T).

As stated above, the AND integrating and holding circuit 50 is identicalto the circuit 40 except that the terminal corresponding to inputterminal 41 has the output of single shot 30 (waveform d) connectedthereto. In addition, the input terminal corresponding to the inputterminal 42a and'terminal 62 has the inverter (Le. waveform b")connected thereto so as to receive the waveform illustrated in FIG.3(b). The output of the single shot 30 is illustrated in FIG. 3(d) andthe pulses T2, T4 and T6 are produced similarly to T1, T3 and T5 so asto effect discharging of a capacitorsimilar to C41 during this period.Thus, contrary to circuit 40, integration and/or discharge of acapacitor occurs during the even transition time periods and morespecifically, during the pulses T2, T4 and T6. After the end of one ofthe pulses P2, P4, etc., and during the odd transition time period, thisintegrated output will be held and gated into the summing point Athrough resistor 71. This gating is effected by the waveform (b) shownin FIG. 3(b) being applied to the analogue gate 70 so as to effectpassing of the waveform (j) shown in FIG. 36) during the odd transitiontime periods to output 80.

Thus, it is seen that during the odd transition time periods, theintegrated output from 50 is applied to summing point A while thecircuit 40 is integrating and the output of 40 and 60 is not beingapplied to summing point A. During the even transition time periods theintegrated output of 40 is applied to the summing point A while circuit50 is integrating. The

output of analogue gate 60, as shown in FIG. 3(i) and the output ofanalogue gate 70, as shown in FIG. 3(j), are shown as summed outputs inFIG. 3(k).

Thus, it is seen that the high speed sampling is not required as inprevious circuits where only one signal is developed. Therefore,expensive filters are not necessary in the embodiment of this invention.0n the contrary, all that is required is a comparatively slow switchingfrom one DC level to another. It

has been found that by so producing a quantized video signal, no filtersare required to prevent FM feed through and the signal can be directlysupplied to a television monitor.

Referring to page 8, line 11, if E is at its high level, T41 willconduct.

While the invention has been particularly shown and described withreference to a preferred embodiment thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formand details may be made therein without departing from the spirit andscope of the invention.

I claim:

l. A circuit for demodulating a frequency modulated input signal having:

a train of pulse widths, said pulse widths defining a plurality ofalternative odd and even transition time periods;

first means developing a first signal with portions of said signalhaving amplitudes developed as a function of the time length ofevenaltemate transition time periods; second means developing a secondsignal with portions of said signal having amplitudes developed as afunction of the time length of odd alternate transition time periods;

and means summing the portions of said first and said second signals,thereby to provide an output consisting alternately of said first signaland said second signal.

2. A circuit as set forth in claim I wherein said first means developssaid first signal during the even alternate transition time periods andholds the same amplitude during the odd alternate transition timeperiods; and said second means develops the second signal during the oddalternate transition time periods and holds its amplitude during theeven alternate transition time periods.

3. A circuit as set forth in claim 2 wherein said summing means includesgating means to alternately apply to the output, said first signalduring the odd alternate transition time periods and said second signalduring the even alternate transition time periods.

4. A circuit as set forth in claim 3 wherein said first means developssaid first signal having an amplitude which is a function of the timelength of even alternate transition time period less a constant timelength and said second means develops said second signal, the amplitudeof which is a function of the time length of odd alternate transitiontime periods less a constant time length.

5. A circuit as set forth in claim 4 wherein said first means includesan integrator for integrating the time length of even alternatetransition time periods less a constant time length and said secondmeans includes an integrator for integrating the time length of oddalternate transition time periods less a constant time length.

1. A circuit for demodulating a frequency modulated input signal having:a train of pulse widths, said pulse widths defining a plurality ofalternative odd and even transition time periods; first means developinga first signal with portions of said signal having amplitudes developedas a function of the time length of even alternate transition timeperiods; second means developing a second signal with portions of saidsignal having amplitudes developed as a function of the time length ofodd alternate transition time periods; and means summing the portions ofsaid first and said second signals, thereby to provide an outputconsisting alternately of said first signal and said second signal.
 2. Acircuit as set forth in claim 1 wherein said first means develops saidfirst signal during the even alternate transition time periods and holdsthe same amplitude during the odd alternate transition time periods; andsaid second means develops the second signal during the odd alternatetransition time periods and holds its amplitude during the evenalternate transition time periods.
 3. A circuit as set forth in claim 2wherein said summing means includes gating means to alternately apply tothe output, said first signal during the odd alternate transition timeperiods and said second signal during the even alternate transition timeperiods.
 4. A circuit as set forth in claim 3 wherein said first meansdevelops said first signal having an amplitude which is a function ofthe time length of even alternate transition time period less a constanttime length and said second means develops said second signal, theamplitude of which is a function of the time length of odd alternatetransition time periods less a constant time length.
 5. A Circuit as setforth in claim 4 wherein said first means includes an integrator forintegrating the time length of even alternate transition time periodsless a constant time length and said second means includes an integratorfor integrating the time length of odd alternate transition time periodsless a constant time length.